Bug 698 - ls180 ASIC test tasks
Summary: ls180 ASIC test tasks
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Hardware Layout (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
Depends on: 383
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Reported: 2021-09-17 09:26 BST by Luke Kenneth Casson Leighton
Modified: 2022-07-21 13:47 BST (History)
6 users (show)

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Description Luke Kenneth Casson Leighton 2021-09-17 09:26:17 BST
>>  * clock reference for PLL
>>  * Clock multiplier selection for PLL
>>  * reset
>>  * JTAG
>>      o Test outputs directly with boundary scan
>>      o drive internal memory mapped peripherals directly without
>>        needing CPU
>>      o test on-chip memory; load programs into it
>>  * GPIO

equipment needed:

* BNC Digital scope (FPGA?)
* BNC Digital clock generator (FPGA)
* Voltage Controlled Oscillator Generator (BNC)
* 3.3v supply
* 1.8v supply
* JTAG output (FT232 is sufficient)


* https://lists.libre-soc.org/pipermail/libre-soc-dev/2021-October/003950.html
* https://lists.libre-soc.org/pipermail/libre-soc-dev/2021-September/003729.html
* https://libre-soc.org/180nm_Oct2020/ls180.svg
* https://ftp.libre-soc.org/course_18oct2021/
Comment 1 Luke Kenneth Casson Leighton 2021-10-27 12:26:06 BST
here is the diagram for the pinouts, it was auto-generated
by the pinmux program


* the IO rail is 3.3v
* the core rail is 1.8v
* P_SYS_PLLCLK (N29) is a *digital* input clock (can be generated by FPGA
  or by signal generator)
* the P_SYS_CLKSEL_0 (N30) and P_SYS_CLKSEL_1 (N31) if set LO
  will route the digital input clock directly to sys_clk

JTAG can be done by openocd using an FT232, configuration setup description
and options are here:


we colour-coded the FT232 pins:


there is "firmware upload" software written in python that connects
to jtagremote (openocd can be put into "jtagremote" mode):


there is more in that same directory.

and there is openocd commands for running some rudimentary SVF files
and also openocd.cfg for using with FT232 


Comment 2 Staf Verhaegen 2021-10-27 17:54:45 BST
I think a block diagram of the SoC and a memory map of the IP blocks would also come handy during testing.
Comment 3 Luke Kenneth Casson Leighton 2021-10-27 20:24:33 BST
(In reply to Staf Verhaegen from comment #2)
> I think a block diagram of the SoC and a memory map of the IP blocks would
> also come handy during testing.

good point.  fortunately, very recently, the IBM India sponsored Educational
Course on OpenPOWER is running, the diagrams are here (and now in comment #0)

diagrams 1 and 4 are the most useful.  memory map: basically autogenerated
by litex so needs to be "dug out" of the build process information, beyond
that, the one thing i made sure was that the UART was at the exact same
memory address as Microwatt.

oh, also, the boundary scan order.  manuel i must apologise, there was not
enough time to put it into "pinout sequential order", however hmm now that
i think about it, i can probably get the pinouts svg-generator program to
at least print out the offset and IOType.  or, update the program that
generated the pinouts page


hmmm although i now realise, those are the die pinouts, not the *package*
pinouts, although there is a programmatic map for them in the autogeneration
of the SVG, i haven't had time to include that in the autogenerated
ls180.mdwn file

the offset and IOType is defined (python source code) here:

 163 class IOConn(Record):
 164     lengths = {
 165         IOType.In: 1,
 166         IOType.Out: 1,
 167         IOType.TriOut: 2,
 168         IOType.InTriOut: 3,

yes, really, python to define HDL JTAG Boundary Scan Registers :)

i will dig up the sequence somehow, so that you know if you set JTAG
register X to 0b000100.... it sets a certain (expected) pad.
Comment 4 Luke Kenneth Casson Leighton 2022-03-26 14:17:37 GMT
from Jean-Paul:

  Hello All,

  I'm very pleased to announce you that Dimitri conducted some
  preliminary tests showing that the PLL is working. He did only
  have a 20MHz clock generator so it's not yet confirmed to
  work at nominal speed, but still. He will process with the
  right clock generator next Monday.

  Best regards,
      .-.     J e a n - P a u l   C h a p u t  /  Administrateur
Comment 5 Luke Kenneth Casson Leighton 2022-07-21 13:47:11 BST

ahh component sourcing, deep joy. can you put the part characteristics on the bugtracker
i will have a look.  current voltage frequency etc.

the CPU is programmable only by JTAG which is Microwatt DMI Interface.


full JTAG Boundary Scan also added.


yes really, that simple (not so much in litex which was 3 months hell)

> My colleagues from LIP6 are willing to test basic functionalities of the chip through JTAG interface. I guess for that they need a digital analyser, a digital wayform generator and/or a FPGA board.

openocd id check should work fine.