Bug 65 - variable-width in / variable-width out queue needed
Summary: variable-width in / variable-width out queue needed
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 62
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Reported: 2019-04-19 09:16 BST by Luke Kenneth Casson Leighton
Modified: 2021-10-02 11:30 BST (History)
1 user (show)

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NLnet milestone: NLnet.2019.02.012
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Description Luke Kenneth Casson Leighton 2019-04-19 09:16:05 BST 
in many scenarios, data comes in at a different speed or bitrate from
the speed or bitwidth at which it goes out.  examples:

* UART handling.  data comes in bit-wise, goes out byte-wise
* SATA 8/10 checksum and handling.  data comes in bitwise, is checked, bytes-out
* Wishbone / AXI4 bridges: data comes in 64-bit, goes out 16-bit
* instruction buffer: data comes in on cache-line width, goes out 16/32/48/64

this latter is more complex in that the data needs to be inspected
intrusively in order to ascertain how much will go out.