similar to chisel3 util and not quite as generally along the lines of litex, and augmenting nmigen.lib, a data handling, i/o control, pipeline-building-block, queues (FIFOs) and general utils library is needed. two key pieces of information to decide: * name of the repo * name (hierarchy) in python Subtasks (edit this comment to add, and create sub-bug): * bug #63 queue (FIFO) with write-through and support for 1-address entries * bug #65 variable-length IN, variable-length OUT queue * bug #64 data handling and routing, i/o control and synchronisation * bug #68 general small utility routines * bug #66 nmigen Object class needed (python inheritance) * bug #132 general-purpose nmigen SIMD (Partitioned Signal) links: * https://github.com/m-labs/nmigen/tree/master/nmigen/lib * https://chisel.eecs.berkeley.edu/api/3.0.1/chisel3/util/Queue.html * https://github.com/freechipsproject/chisel3/tree/src/main/scala/chisel3/util * https://github.com/enjoy-digital/litex/blob/master/litex/gen/common.py
we need a decision on the name of the library and the name of the git repository.