Bug 807 - WB64to32Convert spurious ACK during master STALL in burst transfer
Summary: WB64to32Convert spurious ACK during master STALL in burst transfer
Status: RESOLVED INVALID
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Other
: --- normal
Assignee: tpearson
URL:
Depends on:
Blocks: 806
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Reported: 2022-04-11 18:33 BST by tpearson
Modified: 2022-04-16 18:14 BST (History)
2 users (show)

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Description tpearson 2022-04-11 18:33:06 BST 
The WB64to32Convert module does not obey a master stall request during burst transfers per the Wishbone specification.  When the master attempts to stall the slave during a burst transfer, the slave may attempt to send one beat of data (a single spurious ACK) before finally recognizing the master is in a STALL condition.  If this happens, the data transfer to the master is lost / corrupted for compliant masters.

Unfortunately, a second bug in the Icache module has masked this problem, and it took a while to figure out why inserting a new bridge controller between the ICache and the WB64to32Convert wasn't working.
Comment 1 tpearson 2022-04-11 18:44:57 BST 
Fixed in ls2 GIT hash 91a0c43 (ddr3 branch)
Comment 2 Luke Kenneth Casson Leighton 2022-04-11 18:54:50 BST 
(In reply to tpearson from comment #1)
> Fixed in ls2 GIT hash 91a0c43 (ddr3 branch)

https://git.libre-soc.org/?p=ls2.git;a=commitdiff;h=91a0c4363cbd62ff506bcaad2ee7f57d42b28c7d

yyyeah don't get me started, i lost about 2 months searching
for bugs here.
Comment 3 Luke Kenneth Casson Leighton 2022-04-16 18:14:47 BST 
again invalid just as with bug #808, WB4 Pipe connecting to WB3 classic
has to be done with extreme care.