The ICache module appears to unconditionally accept all ACKs from the connected Wishbone slave and treat them as valid data transfers, even if the bus is in a STALL state. I am unclear as to whether this is intentional, but it does mask specific types of non-compliancy in connected peripherals, e.g. that seen in bug 807.
any chance if you could do a screenshot of gtkwave traces with arrows pointing at where-it-goes-wrong? with icache.py being an exact duplication of icache.vhdl this will be a bug in microwatt as well.
Sure, give me a bit to get the async bridges for #806 finished first. They show the problem quite nicely with the fix for #807 reverted.
declaring this one invalid because WB3 classic master cannot drive WB4 pipe slave. WB4 Pipe stb *has* to be behind WB4 pipe ack (by at least 1 clock) where if stall is set it will be longer than 1 clock.