first phase: * research and documentation * preliminary implementation (including minor unit tests) * evaluation and addition of ALUs * comprehensive unit test suite * formal verification second phase: * addition of FP ALUs * addition of LD/ST Matrix * addition of branch prediction * addition of exceptions / interrupts (sub-phases for each: unit tests, formal verification) third phase: * addition of precise "nameless" Q-Table history * addition of SIMD ALUs * addition of vectorisation (multi-issue OoO elements) * addition of "hierarchical cascade" (64/32/16/8-bit) hazards (sub-phases for each: unit tests, formal verification)
discussion / links (edit as appropriate, add new links as-and-when) * https://groups.google.com/a/groups.riscv.org/forum/#!topic/hw-dev/b4pPvlzBzu0
Created attachment 12 [details] clarification of LD/ST dependency cell WAR and RAW are unclocked SR-Latches
Created attachment 13 [details] clarification of LD/ST Function Unit logic SR Latches apparently don't like both inputs being ASSERTED, seeking clarification from mitch on the use of a single SRLatch
first revision of modules from mitch alsup book chapters now created, with a high-level exploratory unit test created, currently being debugged. it appears that there are combinatorial loops involving busy/issue on SRLatches, which are being investigated. a single "add", once a delay is added, seems to be successful.
https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/9nn4haAuAQAJ https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/experiment/cscore.py;h=be085c51ad814c02c5446616168659767b6bdfd8;hb=1cc0064235ffaa9cea2439e2c9e92f5711b7dc1c is now functional, and has been tested several times with up to 100 random instructions. caveats described in the above post to hw-dev.
LDSTCompUnit basic unit test now works: two STs followed by two LDs will return the correct data from the LDs, and the ADD and ADD-immediate i've confirmed also work. the next phase is to use these in the score6600.py experiment and see if the "instructions" result in actual LDs and STs.
managed to get LDSTCompUnit operational in score6600.py, needs more investigation and checking, including more significant unit tests.