Bug 824 - Adding wire RC to the layout extractor (Solstice)
Summary: Adding wire RC to the layout extractor (Solstice)
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's second ASIC
Classification: Unclassified
Component: source code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Jean-Paul Chaput
URL:
Depends on:
Blocks:
 
Reported: 2022-04-29 16:01 BST by Jean-Paul Chaput
Modified: 2023-02-12 12:08 GMT (History)
2 users (show)

See Also:
NLnet milestone: NLnet.2021-08-049.coriolis2
total budget (EUR) for completion of task and all subtasks: 3000
budget (EUR) for this task, excluding subtasks' budget: 3000
parent task for budget allocation: 748
child tasks for budget allocation:
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Description Jean-Paul Chaput 2022-04-29 16:01:50 BST 
Adding limited electrical information extraction (wire resistance and capacitance) to the new layout extractor (Solstice).