Bug 748 - NLnet toplevel Milestone 2021-08-049 coriolis2
Summary: NLnet toplevel Milestone 2021-08-049 coriolis2
Alias: None
Product: Libre-SOC's second ASIC
Classification: Unclassified
Component: source code (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL: https://libre-soc.org/nlnet_2021_lip6...
Depends on:
Reported: 2021-11-20 16:29 GMT by Luke Kenneth Casson Leighton
Modified: 2022-05-12 14:28 BST (History)
5 users (show)

See Also:
NLnet milestone: NLnet.2021-08-049.coriolis2
total budget (EUR) for completion of task and all subtasks: 50000
budget (EUR) for this task, excluding subtasks' budget: 11000
parent task for budget allocation:
child tasks for budget allocation: 799 800 819 820 822 823 824 825
The table of payments (in EUR) for this task; TOML format:


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Description Luke Kenneth Casson Leighton 2021-11-20 16:29:12 GMT
top level milestone for coriolis2 NLnet grant 2021-08-049

milestones TODO:

# hold violation
  - insert buffers in between two flip-flops
    (stops clock skew) to delay the signal on paths that are too
  - estimated: 1 month
  - EUR 2500
  - https://bugs.libre-soc.org/show_bug.cgi?id=799

* to add LVS capability,
  - porting and updating of older (Alliance) layout extractor tools
    (solstice, equinox) to newer (c++/python) coriolis2 as pure
    netlist extractor:
  - PRIORITY: resistance and capacitance extraction.
  - 2 months
  - EUR 6000
  - https://bugs.libre-soc.org/show_bug.cgi?id=800

* SPICE extractor
  - SPICE LVS transistor level extractor from Cell Libraries
    (reorder pins in correct interface order)
  - 3-4 weeks
  - EUR 3000

* integrate the Static Timing Analysis tool (HITAS) and YAGLE gate-level
  extraction tool,
  - HITAS/YAGLE integration into coriolis2, updating license and
    documentation: autobuild scripts as well
  - update cmake
  - 4 weeks
  - EUR 2500
  - https://bugs.libre-soc.org/show_bug.cgi?id=820

* researching Logical Equivalence algorithms and Academic papers to
  ensure good knowledge before proceeding:
  - documenting the available research and decision:
  - 4 to 5 weeks.
  - EUR 3000
  - https://bugs.libre-soc.org/show_bug.cgi?id=822

* implementation of Logical Equivalence checker:
  - this is **not** the same as an **extraction** tool (above). the LEQ tool
    **uses** (checks) the extracted database.
  - 10 to 14 weeks.
  - EUR 9000
  - https://bugs.libre-soc.org/show_bug.cgi?id=823

* validation of Logical Equivalence checker against simulations and
  other (proprietary) checkers:
  - 6 to 8 weeks
  - documentation and integration of Mitch's LEQ Checker with coriolis2?
  - https://github.com/d-m-bailey/cvc
  - EUR 5000

* to complete the conversion to python 3,
  - porting to python3 (some libraries have to be
    removed and rewritten) including re-running several designs and
    checking they are still the same.
  - 3 months estimated (2 month remaining)
  - EUR 7000
  - https://bugs.libre-soc.org/show_bug.cgi?id=819

medium priority:

* adding limited electrical information extraction (wire resistance
  and capacitance) to the new layout extractor:
  - 4-6 weeks
  - EUR 3000
  - https://bugs.libre-soc.org/show_bug.cgi?id=824

* improve the internal data format (to better handle mixed case
  module and signal names),
  - probably Verilog, because it supports case-sensitive naming
  - (other option: yosys rtlil)
  - another option FIRRTL
  - alternative file formats and data structures which support
    case-sensitive net names
  - 2 months
  - EUR 6000
  - https://bugs.libre-soc.org/show_bug.cgi?id=825

lower priority:
* To improve the speed of the GUI front-end,
  - 1 month?
  - EUR 1000

* documentation and integration of coriolis2 into efabless?
  - reading of user DEF project file
  - EUR 2000?


covered by NGI POINTER?

* to make it possible to handle larger ASIC designs,
  - multiple adhoc clock trees
  - to try smaller geometry ASICs (beginning with 130nm),
  - 2 months?

* nix package management of coriolis2
  - TODO (actually, done?)
Comment 1 Luke Kenneth Casson Leighton 2021-11-20 16:36:28 GMT
meeting with NLnet tue 23rd at 12:00 CET/Paris/Amsterdam 13:00 UTC
to discuss milestones.  best to have some outline before then!
Comment 2 Luke Kenneth Casson Leighton 2021-11-20 22:27:38 GMT

although there is a backend (writer) for firrtl there is no frontend (reader)
the format looks very clear, well documented, stable, and, crucially,
has a strict subset format "LoFIRRTL" (Chap 11)


note: FIRRTL is a whitespace indentation syntax, it is NOT possible
for yacc LALR to cope with that, but lex can, with a special pre-parse
lexer phase adding in hidden INDENT and DEDENT tokens.  this is done
here, in python:

Comment 3 Jean-Paul Chaput 2021-11-23 12:44:12 GMT
(In reply to Luke Kenneth Casson Leighton from comment #1)
> meeting with NLnet tue 23rd at 12:00 CET/Paris/Amsterdam 13:00 UTC
> to discuss milestones.  best to have some outline before then!


1. The full scale thing is based upon the hypothesis that we will be able
   to hire our internship. Looked interested, but still.

2. Do not want to make a transistor level LVS for gates. Just read
   correctly the pin order, so we don't have to use a "wrapper"

3. Need to be more clear about the concept of "porting" HiTas/Yagle.
   No real development work involved here. Just updating the licenses,
   migrating to CMake and just a minimum of code cleanup/upgrade
   to compile on recent systems (even that *may* takes time).

4. LEQ: Do we include the "resynthesis case" ? (way more complex, because
   we need to manage booleans equations).

5. GUI frontend now works at a bearable speed, even if it still may be
   improved (remove the complex double buffering maybe).

6. Efabless : if it's about the support of the harness, will do it
   anyway, and quickly (for ChipFlow/Staf and general use).

7. Protection againts hold violations (basic buffer insertion).

8. Mutliple clocks domains, localized clock tree : NGI pointer.

9. Separation between what the internship will do and I will do not 
   clear at this stage. But, in all case the money must go the intern.
Comment 4 Luke Kenneth Casson Leighton 2021-11-23 13:13:58 GMT

timing closure

* hold violation

* logical extraction (router did its job, exactly equal to spec netlist)
  *with* timing extraction (resistor capacitor)
  to generate SPICE netlist, not full design, but only on selected nets
  that may cause problems: just simulate those

hold violation:

* insert buffers in between two flip-flops
  (stops clock skew) to delay the signal on paths that are too

  estimated: 1 month

  - EUR 2500