top level milestone for coriolis2 NLnet grant 2021-08-049 milestones TODO: # hold violation - insert buffers in between two flip-flops (stops clock skew) to delay the signal on paths that are too short. - estimated: 1 month - EUR 2500 - https://bugs.libre-soc.org/show_bug.cgi?id=799 * to add LVS capability, - porting and updating of older (Alliance) layout extractor tools (solstice, equinox) to newer (c++/python) coriolis2 as pure netlist extractor: - PRIORITY: resistance and capacitance extraction. - 2 months - EUR 6000 - https://bugs.libre-soc.org/show_bug.cgi?id=800 * SPICE extractor - SPICE LVS transistor level extractor from Cell Libraries (reorder pins in correct interface order) - 3-4 weeks - EUR 3000 - URL TODO * integrate the Static Timing Analysis tool (HITAS) and YAGLE gate-level extraction tool, - HITAS/YAGLE integration into coriolis2, updating license and documentation: autobuild scripts as well - update cmake - 4 weeks - EUR 2500 - https://bugs.libre-soc.org/show_bug.cgi?id=820 * researching Logical Equivalence algorithms and Academic papers to ensure good knowledge before proceeding: - documenting the available research and decision: - 4 to 5 weeks. - EUR 3000 - https://bugs.libre-soc.org/show_bug.cgi?id=822 * implementation of Logical Equivalence checker: - this is **not** the same as an **extraction** tool (above). the LEQ tool **uses** (checks) the extracted database. - 10 to 14 weeks. - EUR 9000 - https://bugs.libre-soc.org/show_bug.cgi?id=823 * validation of Logical Equivalence checker against simulations and other (proprietary) checkers: - 6 to 8 weeks - documentation and integration of Mitch's LEQ Checker with coriolis2? - https://github.com/d-m-bailey/cvc - EUR 5000 - URL TODO * to complete the conversion to python 3, - porting to python3 (some libraries have to be removed and rewritten) including re-running several designs and checking they are still the same. - 3 months estimated (2 month remaining) - EUR 7000 - https://bugs.libre-soc.org/show_bug.cgi?id=819 medium priority: * adding limited electrical information extraction (wire resistance and capacitance) to the new layout extractor: - 4-6 weeks - EUR 3000 - URL TODO - https://bugs.libre-soc.org/show_bug.cgi?id=824 * improve the internal data format (to better handle mixed case module and signal names), - probably Verilog, because it supports case-sensitive naming - (other option: yosys rtlil) - another option FIRRTL https://github.com/chipsalliance/firrtl/blob/master/spec/spec.pdf - alternative file formats and data structures which support case-sensitive net names - 2 months - EUR 6000 - https://bugs.libre-soc.org/show_bug.cgi?id=825 lower priority: * To improve the speed of the GUI front-end, - 1 month? - EUR 1000 - URL TODO * documentation and integration of coriolis2 into efabless? - reading of user DEF project file - EUR 2000? - URL TODO ==== BELOW THIS POINT, NOT PART OF Schedule A MOU === covered by NGI POINTER? * to make it possible to handle larger ASIC designs, - multiple adhoc clock trees - to try smaller geometry ASICs (beginning with 130nm), - 2 months? * nix package management of coriolis2 - TODO (actually, done?)
meeting with NLnet tue 23rd at 12:00 CET/Paris/Amsterdam 13:00 UTC to discuss milestones. best to have some outline before then!
https://github.com/YosysHQ/yosys/blob/master/backends/firrtl/firrtl.cc although there is a backend (writer) for firrtl there is no frontend (reader) the format looks very clear, well documented, stable, and, crucially, has a strict subset format "LoFIRRTL" (Chap 11) https://github.com/YosysHQ/yosys/issues/2004 https://github.com/boqwxp/yosys/tree/frontend-firrtl/frontends/firrtl note: FIRRTL is a whitespace indentation syntax, it is NOT possible for yacc LALR to cope with that, but lex can, with a special pre-parse lexer phase adding in hidden INDENT and DEDENT tokens. this is done here, in python: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/lexer.py;h=b420798b17533118a8440e91c077b38f2b68180f;hb=a17a252e474d5d5bf34026c25a19682e3f2015c3#l183
(In reply to Luke Kenneth Casson Leighton from comment #1) > meeting with NLnet tue 23rd at 12:00 CET/Paris/Amsterdam 13:00 UTC > to discuss milestones. best to have some outline before then! Questions ========= 1. The full scale thing is based upon the hypothesis that we will be able to hire our internship. Looked interested, but still. 2. Do not want to make a transistor level LVS for gates. Just read correctly the pin order, so we don't have to use a "wrapper" level. 3. Need to be more clear about the concept of "porting" HiTas/Yagle. No real development work involved here. Just updating the licenses, migrating to CMake and just a minimum of code cleanup/upgrade to compile on recent systems (even that *may* takes time). 4. LEQ: Do we include the "resynthesis case" ? (way more complex, because we need to manage booleans equations). 5. GUI frontend now works at a bearable speed, even if it still may be improved (remove the complex double buffering maybe). 6. Efabless : if it's about the support of the harness, will do it anyway, and quickly (for ChipFlow/Staf and general use). 7. Protection againts hold violations (basic buffer insertion). 8. Mutliple clocks domains, localized clock tree : NGI pointer. 9. Separation between what the internship will do and I will do not clear at this stage. But, in all case the money must go the intern.
priorities: timing closure * hold violation * logical extraction (router did its job, exactly equal to spec netlist) *with* timing extraction (resistor capacitor) to generate SPICE netlist, not full design, but only on selected nets that may cause problems: just simulate those hold violation: * insert buffers in between two flip-flops (stops clock skew) to delay the signal on paths that are too short. estimated: 1 month - EUR 2500