Top level milestone for Coriolis2 NLnet grant 2021-08-049 ========================================================= A. Extractor & LVS/LEQ for Coriolis ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ For **Jean-Paul Chaput**. Amount: 16000 EUR * Add LVS capability, - porting and updating of older (Alliance) layout extractor tools (solstice, equinox) to newer (c++/python) coriolis2 as pure netlist extractor: - https://bugs.libre-soc.org/show_bug.cgi?id=800 * SPICE extractor - SPICE LVS transistor level extractor from Cell Libraries (reorder pins in correct interface order) * implementation of Logical Equivalence checker: - this is **not** the same as an **extraction** tool (above). the LEQ tool **uses** (checks) the extracted database. - https://bugs.libre-soc.org/show_bug.cgi?id=823 Repository : **coriolis2**. B. Layout generator of AMS primitive cells ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ For **Marie-Minerve Louërat** et **Dimitri Galayko**. Amount 11000 EUR - Marie-Minerve Louërat: 3000 EUR - Dimitri Galayko: 8000 EUR Design Python generic layout generators (description of the relative placement) of the transistor devices for Analog and Mixed Signal (AMS) primitive cells following the slicing tree approach in Coriolis2. To launch the placement, the sizes can be read from a netlist or from a result file of the FOSS EDA Oceane tool (library of Analog netlist). The list of analog primitives consisting of transistors are: * Operational Transconductance Amplifier (OTA) simple * OTA Miller * Comparator * Biasing cells * Quad CMOS * Bandgap * Voltage Controlled Oscillator (VCO) * Charge pump * Delay cell The list of analog primitives consisting of capacitors are: * Unit capacitor * Capacitor array The list of digital primitives for AMS functions are: * Phase comparator * Frequency divider Repository : **coriolis**. These primitives will be committed in coriolis2 git repository. To validate the primitives, 2 use cases will be provided: * Layout of a SAR ADC (Successive Approximation Register Analog to Digital Converter) * Layout of a PLL (Phase Locked Loop) Repository : **alliance-check-toolkit**. C. Library of symbolic cells for SRAM blocks ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Amount: 6000 EUR For: **Franck Wajsburt**. Cells for buiding SRAM blocks will be designed, compatible with the symbolic to real approach. Repository : **alliance-check-toolkit**. D. Library of standard cells, symbolic to real approach ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Amount: 9000 EUR For: **Marie-Minerve Louërat** and **Franck Wajsburt**. - Marie-Minerve Louërat: 3000 EUR - Franck Wajsburt: 6000 EUR Build a standard cell library, in technology SkyWater130, following the symbolic to real approach, using the scalability of active layers till metal 1 (well, active/diffusion, gate, contact/via0, poly, metal1) and the NSXLIB standard cell library as template. Repository : **alliance-check-toolkit**. E. Coriolis API (RC) ~~~~~~~~~~~~~~~~~~~~ Amount: 8000 EUR For: **Roselyne Chotin**. Build an user API and associated documentation to access and manipulate the circuit’s database (cells, nets etc.) or get information like e.g. net delay or cell fanout to use it from external tools. Benchmark this API on standard circuits (e.g. ISCAS or ITC) with external tools like those developed for security primitives insertion. Repository : **coriolis**.
meeting with NLnet tue 23rd at 12:00 CET/Paris/Amsterdam 13:00 UTC to discuss milestones. best to have some outline before then!
https://github.com/YosysHQ/yosys/blob/master/backends/firrtl/firrtl.cc although there is a backend (writer) for firrtl there is no frontend (reader) the format looks very clear, well documented, stable, and, crucially, has a strict subset format "LoFIRRTL" (Chap 11) https://github.com/YosysHQ/yosys/issues/2004 https://github.com/boqwxp/yosys/tree/frontend-firrtl/frontends/firrtl note: FIRRTL is a whitespace indentation syntax, it is NOT possible for yacc LALR to cope with that, but lex can, with a special pre-parse lexer phase adding in hidden INDENT and DEDENT tokens. this is done here, in python: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/lexer.py;h=b420798b17533118a8440e91c077b38f2b68180f;hb=a17a252e474d5d5bf34026c25a19682e3f2015c3#l183
(In reply to Luke Kenneth Casson Leighton from comment #1) > meeting with NLnet tue 23rd at 12:00 CET/Paris/Amsterdam 13:00 UTC > to discuss milestones. best to have some outline before then! Questions ========= 1. The full scale thing is based upon the hypothesis that we will be able to hire our internship. Looked interested, but still. 2. Do not want to make a transistor level LVS for gates. Just read correctly the pin order, so we don't have to use a "wrapper" level. 3. Need to be more clear about the concept of "porting" HiTas/Yagle. No real development work involved here. Just updating the licenses, migrating to CMake and just a minimum of code cleanup/upgrade to compile on recent systems (even that *may* takes time). 4. LEQ: Do we include the "resynthesis case" ? (way more complex, because we need to manage booleans equations). 5. GUI frontend now works at a bearable speed, even if it still may be improved (remove the complex double buffering maybe). 6. Efabless : if it's about the support of the harness, will do it anyway, and quickly (for ChipFlow/Staf and general use). 7. Protection againts hold violations (basic buffer insertion). 8. Mutliple clocks domains, localized clock tree : NGI pointer. 9. Separation between what the internship will do and I will do not clear at this stage. But, in all case the money must go the intern.
priorities: timing closure * hold violation * logical extraction (router did its job, exactly equal to spec netlist) *with* timing extraction (resistor capacitor) to generate SPICE netlist, not full design, but only on selected nets that may cause problems: just simulate those hold violation: * insert buffers in between two flip-flops (stops clock skew) to delay the signal on paths that are too short. estimated: 1 month - EUR 2500
jean-paul is dealing directly with NLnet on this one.