Currently, Coriolis can only read/write netlist in:

* BLIF, which is completely obsolete and is used *only* because
  it was quicker than to develop a Verilog parser.

* VST, the Alliance VHDL subset, which cannot handle all the valid
  characters in Verilog so we must perform a name mangling which
  muddies the netlist.

To solve that, add a new parser driver so we can directly support
Verilog names. We should choose among the following candidates:

* Verilog (simplified version for netlist) for obvious reasons.
* RTLIL, as the native output format of Yosys, but not ideal for
  other ones.
* FIRRTL
  https://github.com/chipsalliance/firrtl/blob/master/spec/spec.pdf