Bug 825 - Add a new parser/driver able to handle Verilog names
Summary: Add a new parser/driver able to handle Verilog names
Alias: None
Product: Libre-SOC's second ASIC
Classification: Unclassified
Component: source code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Jean-Paul Chaput
Depends on:
Reported: 2022-04-29 16:15 BST by Jean-Paul Chaput
Modified: 2023-02-12 12:08 GMT (History)
2 users (show)

See Also:
NLnet milestone: NLnet.2021-08-049.coriolis2
total budget (EUR) for completion of task and all subtasks: 6000
budget (EUR) for this task, excluding subtasks' budget: 6000
parent task for budget allocation: 748
child tasks for budget allocation:
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Description Jean-Paul Chaput 2022-04-29 16:15:34 BST
Currently, Coriolis can only read/write netlist in:

* BLIF, which is completely obsolete and is used *only* because
  it was quicker than to develop a Verilog parser.

* VST, the Alliance VHDL subset, which cannot handle all the valid
  characters in Verilog so we must perform a name mangling which
  muddies the netlist.

To solve that, add a new parser driver so we can directly support
Verilog names. We should choose among the following candidates:

* Verilog (simplified version for netlist) for obvious reasons.
* RTLIL, as the native output format of Yosys, but not ideal for
  other ones.