Bug 828 - 2RW and 1RW SRAM compiler development
Summary: 2RW and 1RW SRAM compiler development
Alias: None
Product: Libre-SOC's second ASIC
Classification: Unclassified
Component: source code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Staf Verhaegen
Depends on:
Blocks: 690
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Reported: 2022-05-02 14:19 BST by Staf Verhaegen
Modified: 2022-08-02 08:37 BST (History)
2 users (show)

See Also:
NLnet milestone: NGI.POINTER.Gigabit.ASIC
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
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Description Staf Verhaegen 2022-05-02 14:19:15 BST
After designing the SRAM cell in bug #827 the compiler need to be made. This task will consist of the following subtasks:

* layout helper functions in PDKMaster to ease layout
* Update layout of 1RW subblocks for optimized 1RW SRAM cell and 
* Update layout of subblocks to handle double bitline pair for 2RW dual part compiler.
Comment 1 Staf Verhaegen 2022-08-02 08:37:31 BST
The SRAM compiler development will be moved to another LIP6-Chips4Makers cooperation project. Giving more time for completion and focus on other things for NGI Pointer.