Bug 829 - Post-layout verification of ASIC SRAM blocks
Summary: Post-layout verification of ASIC SRAM blocks
Alias: None
Product: Libre-SOC's second ASIC
Classification: Unclassified
Component: source code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Staf Verhaegen
Depends on:
Blocks: 690
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Reported: 2022-05-02 14:29 BST by Staf Verhaegen
Modified: 2022-08-29 23:10 BST (History)
2 users (show)

See Also:
NLnet milestone: NGI.POINTER.Gigabit.ASIC
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Description Staf Verhaegen 2022-05-02 14:29:54 BST
The blocks that will be on the router ASIC and generated by the compilers developed in bug #828 should be verified with simulation and (estimated) parasitics. This is for both the used 1RW and 2RW blocks.
Especially bigger block will need to be verified for race conditions on the internal signals due to the load on the nets.
The effort needed for this exercise will depend on the number of unique blocks and the size of the blocks.