Trying to compile the following code:
# Load 2.0f constant in fpr 1 , will be needed for SHR macro
fmvis c_2, 0x4000
/usr/local/bin/powerpc64le-linux-gnu-as -mlibresoc -mregnames -o imdct36_svp64_real.o imdct36_svp64_real.s
imdct36_svp64_real.s: Assembler messages:
imdct36_svp64_real.s:92: Error: unrecognized opcode: `fmvis'
Similarly for fishmv.
I checked it, these both will need custom handlers. Also, since we want to be good citizens, we must also add tests. Anyway, these don't look as difficult as say svshape2 was, perhaps I'll complete it even today.
(In reply to Dmitry Selyutin from comment #1)
> I checked it, these both will need custom handlers. Also, since we want to
> be good citizens, we must also add tests. Anyway, these don't look as
> difficult as say svshape2 was, perhaps I'll complete it even today.
they're exactly the same as... as... addpcis, which is also DX-Form.
p68 v3.0B. i picked an existing Form very deliberately.
51 # V3.0B 1.6.6 DX-FORM
52 |0 |6 |11 |16 |26 |31
53 | PO | RT| d1| d0| XO|d2
54 | PO | FRS| d1| d0| XO|d2
D <- d0||d1||d2
fmvis FRS, D
bf16 = d0 || d1 || d2 # create BF16 immediate
so the only addition should be using FRS instead of RT.
for the tests you could probably even directly copy the addpcis tests
and just change the instruction name!
Support for fishmv and fmvis has been added; as usual, binutils rebuild is required.
As parent task is completed, I'm marking this as resolved.