Each Draft ISA RFC, once submitted, has to be reviewed for consideration by the OpenPOWER ISA Working Group. This process, for which RED Semiconductor Ltd specifically joined the OPF ISA WG (and is under Commercial Confidentiality), itself has multiple stages, including review by several teams internally within IBM (the primary user of the Power ISA). RED Semiconductor Ltd will take responsibility for collating the questions and ensuring that permission is granted by the ISA WG to publish the questions with neither an NDA nor Commercial Confidentiality being violated, working as a Member of the ISA WG to ensure that no Confidential Information provided by OPF Members becomes public. This is complex! Also involved here may be documenting of modifications to SVP64 and/or the Simulator(s) - the python-based ISACaller and the (new) cavatools 2021-08-071 Grant, bug #939. The documentation of modifications is part of this Milestone: the implementation of changes is not (that should be covered by Grant 2022 08 107, bug #961. * bug #1046 ls001 also now ls001.po9 * bug #1092 ls002 fmis fmi2-4 float-load-immediate * bug #1029 ls003 presentation * bug #1090 ls003.bignum bigint instructions * bug #1062 ls005 XLEN * bug #1069 ls007 ternlog * bug #1089 ls008 management: setvl&svstep * bug #1060 ls009 remap * bug #1056 ls010 svp64 * bug #1054 ls012 summary