Bug 1034 - implement crternlogi crbinlog and binlog in ISACaller
Summary: implement crternlogi crbinlog and binlog in ISACaller
Status: RESOLVED FIXED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: Other Linux
: --- enhancement
Assignee: Dmitry Selyutin
URL: https://libre-soc.org/openpower/sv/bi...
Depends on:
Blocks: 676
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Reported: 2023-03-17 12:06 GMT by Luke Kenneth Casson Leighton
Modified: 2024-05-16 23:39 BST (History)
3 users (show)

See Also:
NLnet milestone: NLnet.2022-08-107.ongoing
total budget (EUR) for completion of task and all subtasks: 3000
budget (EUR) for this task, excluding subtasks' budget: 3000
parent task for budget allocation: 1027
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:
jacob=500 ghostmansd={amount=800, submitted=2024-05-17} lkcl = {amount=1700}


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Description Luke Kenneth Casson Leighton 2023-03-17 12:06:44 GMT
the ternlogi instruction was added to ISACaller with associated unit
tests under the H2020 Grants, the other three in the set are needed.

--

* crternlogi  DONE comment #1 but renamed crfternlogi, new op comment #7
* binlog      DONE comment #2
* crfbinlog   DONE comment #3
* crfternlogi DONE comment #5 comment #6
* crbinlog    DONE comment #15
* spec pages  DONE comment #8, TODO review?
* SVP64       TODO comment #13,
* binutils    TODO

discussion on list

* https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-January/005946.html
Comment 1 Luke Kenneth Casson Leighton 2024-01-17 14:57:20 GMT
added crternlogi, needed for maxloc optimisation.

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=bca969dcae
Comment 2 Luke Kenneth Casson Leighton 2024-01-20 14:26:56 GMT
got binlog unit tests running

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=d42e6e267a1
Comment 3 Luke Kenneth Casson Leighton 2024-01-20 14:59:53 GMT
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=7a3fb5c8a3

had to move maddrs* etc. from PO22 to PO5, as they had
been added in the spots reserved for crbinlut.

all good.
Comment 4 Luke Kenneth Casson Leighton 2024-01-21 20:10:20 GMT
from bug #676 maxlocthe initial instructions planned for crternlogi
are field-based and not sufficient. *bit* based variants are also
needed,and fortunately are quite quick and easy to do. the draft
table of opcodes needs to be re-jigged though
https://libre-soc.org/openpower/sv/draft_opcode_tables/
Comment 5 Luke Kenneth Casson Leighton 2024-01-25 17:45:41 GMT
added crfternlogi and crbinlog

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=4669b4
Comment 6 Luke Kenneth Casson Leighton 2024-01-27 11:17:04 GMT
crfternlogi had to be moved to TLI-Form

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=61e3ef7e
Comment 7 Luke Kenneth Casson Leighton 2024-01-27 12:02:23 GMT
moved crternlogi yet again in PO5 due to large size of operands:

    $ pysvp64db operands crternlogi
    BT 6, 7, 8, 9, 10
    BA 11, 12, 13, 14, 15
    BB 16, 17, 18, 19, 20
    TLI 21, 22, 23, 24, 25, 26, 27, 28

XO is only 3 bits (PO5----110)

    $ pysvp64db opcodes crternlogi
    000101-----------------------110

canonical table is here

    https://libre-soc.org/openpower/sv/draft_opcode_tables/

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=f7b10b60
https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=8c577cf8
Comment 8 Luke Kenneth Casson Leighton 2024-01-27 13:17:22 GMT
updated the spec pages from a copy of openpower/isa/bitmanip.mdwn

https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=69e98b1ff
Comment 9 Luke Kenneth Casson Leighton 2024-01-27 20:19:25 GMT
first version sv.crternlogi but it is only doing one element.
likely a bug in ISACaller (related to CR_OPS)

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=06f576f2
Comment 10 Luke Kenneth Casson Leighton 2024-01-29 13:32:19 GMT
fixing a cut/paste error on crternlogi
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=4bcec8a4
Comment 11 Luke Kenneth Casson Leighton 2024-01-29 13:35:12 GMT
ok so this gets complicated.
https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-January/005990.html

CR Field EXTRA3 encoding can only support vectors starting at
CR0, CR4, CR8, ... CR124

but there are *three* operands (3 vectors needed) to ternary CR field
operations.  that's just not possible to fit within CR0-CR7

i am therefore going to have to cheat slightly and do vector-vector-scalar.
Comment 12 Luke Kenneth Casson Leighton 2024-01-29 14:06:54 GMT
made sv.crternlogi unit test a vector-vector-scalar, but now needs
investigation to make ISACaller support Vector CR fields.
currently it does not do vector-offsets.
Comment 13 Luke Kenneth Casson Leighton 2024-02-02 20:56:04 GMT
hooray, first sv.crternlogi works

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=306bd26a
Comment 14 Luke Kenneth Casson Leighton 2024-02-05 14:40:50 GMT
jacob could you check this is correct? i put a constant
0b0111_1111 into maxloc and it came out *wrong* according
to table 145 xxeval(A,B,C,imm) 

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=c58f6099a
Comment 15 Luke Kenneth Casson Leighton 2024-02-05 21:13:01 GMT
added unit test for crbinlog

https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=0c2419c7f3
Comment 16 Dmitry Selyutin 2024-02-26 18:29:16 GMT
binutils "manual" part is missing, will handle it soon: hopefully this should be easy.
Comment 17 Dmitry Selyutin 2024-02-26 19:07:22 GMT
OK this will be more difficult that I thought, since there must be multiple instructions plus new fields for binutils. I'm postponning this for now, this will be handled sometime along with #1150, #1183 and #1079 and probably others.
Comment 18 Dmitry Selyutin 2024-02-26 19:08:01 GMT
I also assume you mean crbinLOG, not crbinLUT in the subject, right?
Comment 19 Luke Kenneth Casson Leighton 2024-02-26 22:28:09 GMT
(In reply to Dmitry Selyutin from comment #18)
> I also assume you mean crbinLOG, not crbinLUT in the subject, right?

yes. i misnamed them some time ago, keep getting confused.
assigning extra budget to you.
Comment 20 Dmitry Selyutin 2024-02-29 16:46:34 GMT
ternlogi-like instructions are completed:
https://git.libre-soc.org/?p=binutils-gdb.git;a=commitdiff;h=1e5e407fb96b32e94e10add99f803641233869e7

These were especially annoying and weird due to the fact that in reality we have two different TLI, plus crternlogi uses less bits in its opcode. Plus I really already forgot how complex adding instructions to binutils is: few months with no practice. :-)

Moving on with crbinlog.
Comment 21 Dmitry Selyutin 2024-02-29 16:52:33 GMT
```
+/* An MM form instruction with explicit FMM. */
+#define MMXFMM(op, xop, fmm, rc)               \
+  (OP (op)                                     \
+   | ((((uint64_t)(fmm)) & 0xf) << 7)          \
+   | ((((uint64_t)(xop)) & 0x3f) << 1)         \
+   | (((uint64_t)(rc)) & 1))
+#define MMXFMM_MASK    MMXFMM (0x3f, 0x3f, 0xf, 0x1)
```

...these appeared as part of the rebase. Can be ignored, the patches have to be cleaned up later anyway (and partially dropped if we ever move to generating this mess).
Comment 22 Dmitry Selyutin 2024-02-29 17:15:14 GMT
Fixed mask for crternlogi, now it's clear the opcode must be 0b110
Comment 24 Dmitry Selyutin 2024-02-29 18:35:16 GMT
Nice, binlog and friends turned out much simpler. We already had BM2, for the rest I followed ternlogi.

https://git.libre-soc.org/?p=binutils-gdb.git;a=commitdiff;h=2b84a8ee7068fdae4886164ee3806420db39d6dc

I think these two commits make the task completed. Any objections?
Comment 25 Jacob Lifshay 2024-02-29 18:45:18 GMT
(In reply to Dmitry Selyutin from comment #24)
> https://git.libre-soc.org/?p=binutils-gdb.git;a=commitdiff;
> h=2b84a8ee7068fdae4886164ee3806420db39d6dc
> 
> I think these two commits make the task completed. Any objections?

looks good to me!