the ternlogi instruction was added to ISACaller with associated unit tests under the H2020 Grants, the other three in the set are needed. -- * crternlogi DONE comment #1 but renamed crfternlogi, new op comment #7 * binlog DONE comment #2 * crfbinlog DONE comment #3 * crfternlogi DONE comment #5 comment #6 * crbinlog DONE comment #15 * spec pages DONE comment #8, TODO review? * SVP64 TODO comment #13, * binutils TODO discussion on list * https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-January/005946.html
added crternlogi, needed for maxloc optimisation. https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=bca969dcae
got binlog unit tests running https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=d42e6e267a1
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=7a3fb5c8a3 had to move maddrs* etc. from PO22 to PO5, as they had been added in the spots reserved for crbinlut. all good.
from bug #676 maxlocthe initial instructions planned for crternlogi are field-based and not sufficient. *bit* based variants are also needed,and fortunately are quite quick and easy to do. the draft table of opcodes needs to be re-jigged though https://libre-soc.org/openpower/sv/draft_opcode_tables/
added crfternlogi and crbinlog https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=4669b4
crfternlogi had to be moved to TLI-Form https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=61e3ef7e
moved crternlogi yet again in PO5 due to large size of operands: $ pysvp64db operands crternlogi BT 6, 7, 8, 9, 10 BA 11, 12, 13, 14, 15 BB 16, 17, 18, 19, 20 TLI 21, 22, 23, 24, 25, 26, 27, 28 XO is only 3 bits (PO5----110) $ pysvp64db opcodes crternlogi 000101-----------------------110 canonical table is here https://libre-soc.org/openpower/sv/draft_opcode_tables/ https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=f7b10b60 https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=8c577cf8
updated the spec pages from a copy of openpower/isa/bitmanip.mdwn https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=69e98b1ff
first version sv.crternlogi but it is only doing one element. likely a bug in ISACaller (related to CR_OPS) https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=06f576f2
fixing a cut/paste error on crternlogi https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=4bcec8a4
ok so this gets complicated. https://lists.libre-soc.org/pipermail/libre-soc-dev/2024-January/005990.html CR Field EXTRA3 encoding can only support vectors starting at CR0, CR4, CR8, ... CR124 but there are *three* operands (3 vectors needed) to ternary CR field operations. that's just not possible to fit within CR0-CR7 i am therefore going to have to cheat slightly and do vector-vector-scalar.
made sv.crternlogi unit test a vector-vector-scalar, but now needs investigation to make ISACaller support Vector CR fields. currently it does not do vector-offsets.
hooray, first sv.crternlogi works https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=306bd26a
jacob could you check this is correct? i put a constant 0b0111_1111 into maxloc and it came out *wrong* according to table 145 xxeval(A,B,C,imm) https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=c58f6099a
added unit test for crbinlog https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=0c2419c7f3
binutils "manual" part is missing, will handle it soon: hopefully this should be easy.
OK this will be more difficult that I thought, since there must be multiple instructions plus new fields for binutils. I'm postponning this for now, this will be handled sometime along with #1150, #1183 and #1079 and probably others.
I also assume you mean crbinLOG, not crbinLUT in the subject, right?
(In reply to Dmitry Selyutin from comment #18) > I also assume you mean crbinLOG, not crbinLUT in the subject, right? yes. i misnamed them some time ago, keep getting confused. assigning extra budget to you.
ternlogi-like instructions are completed: https://git.libre-soc.org/?p=binutils-gdb.git;a=commitdiff;h=1e5e407fb96b32e94e10add99f803641233869e7 These were especially annoying and weird due to the fact that in reality we have two different TLI, plus crternlogi uses less bits in its opcode. Plus I really already forgot how complex adding instructions to binutils is: few months with no practice. :-) Moving on with crbinlog.
``` +/* An MM form instruction with explicit FMM. */ +#define MMXFMM(op, xop, fmm, rc) \ + (OP (op) \ + | ((((uint64_t)(fmm)) & 0xf) << 7) \ + | ((((uint64_t)(xop)) & 0x3f) << 1) \ + | (((uint64_t)(rc)) & 1)) +#define MMXFMM_MASK MMXFMM (0x3f, 0x3f, 0xf, 0x1) ``` ...these appeared as part of the rebase. Can be ignored, the patches have to be cleaned up later anyway (and partially dropped if we ever move to generating this mess).
Fixed mask for crternlogi, now it's clear the opcode must be 0b110
https://git.libre-soc.org/?p=binutils-gdb.git;a=commitdiff;h=611abbf04e5f359d0c14642dad58429ced89ed7d
Nice, binlog and friends turned out much simpler. We already had BM2, for the rest I followed ternlogi. https://git.libre-soc.org/?p=binutils-gdb.git;a=commitdiff;h=2b84a8ee7068fdae4886164ee3806420db39d6dc I think these two commits make the task completed. Any objections?
(In reply to Dmitry Selyutin from comment #24) > https://git.libre-soc.org/?p=binutils-gdb.git;a=commitdiff; > h=2b84a8ee7068fdae4886164ee3806420db39d6dc > > I think these two commits make the task completed. Any objections? looks good to me!