Research and discussion is needed before an RFC to add new instructions to the Power ISA is needed. Sometimes an instruction, if added, is just not used enough to make it worthwhile. Others might be so specific that they have very limited use-cases. Thus research is required to provide justification for every instruction proposed. note that work done prior to 25oct2022 is EXCLUDED and thus ls001-3 may not be applied for under this milestone. This toplevel milestone will be broken down on an ongoing basis into per-RFC Research bugreports. Table of bugreports: * bug #1074 twin butterfly * bug #926 add-carry from CR Field * bug #996 shaddsw * bug #1016 int/fp mv * bug #1023 crternlut analysis * bug #1043 DCT REMAP * bug #1049 ldst postinc * bug #1051 ls012 research * bug #1053 separate CR regfiles * bug #1063 remove predicate-result
in case this task gets assigned more funding, we could work on the part of bug #937 about adding variable svoffset for dynamic bigint shifts