Bug 11 - Wishbone Interface / Bridge
Summary: Wishbone Interface / Bridge
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on: 468
Blocks: 2 383
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Reported: 2018-02-27 00:27 GMT by Luke Kenneth Casson Leighton
Modified: 2020-09-06 09:52 BST (History)
2 users (show)

See Also:
NLnet milestone: NLnet.2019.02
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:


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Description Luke Kenneth Casson Leighton 2018-02-27 00:27:48 GMT
http://libre-riscv.org/shakti/m_class/wishbone/
Comment 1 Luke Kenneth Casson Leighton 2020-07-12 16:29:38 BST
nmigen-soc contains the required code