the layout of eth_mac (and PLL?) needs Static Timing Analysis of both tsmc 180nm and sky130.
although TSMC 180nm is NDA'd sky130 is not. therefore reproduceability on this should be possible, and all software and data made available for at least sky130. we do not yet have dev-scripts for HITAS/Yagle so that will be needed. Marie I will find someone to handle that. Andrey, how about it? about: https://www-soc.lip6.fr/equipe-cian/logiciels/tasyagle/ source: https://gitlab.lip6.fr/vlsi-eda/tas-yagle devscripts repo: https://git.libre-soc.org/?p=dev-env-setup.git;a=summary
(In reply to Luke Kenneth Casson Leighton from comment #1) > we do not yet have dev-scripts for HITAS/Yagle so that will be needed. > Marie I will find someone to handle that. Andrey, how about it? Will do. Created the initial script and wiki page, currently setting up. https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=ee01d9a5680682fa4bafaf0e314e4ffe9c43eb90 https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=f123c4b478e02fcd0d5dd9812b15ab8c54410fa1 The iwiki page is here: https://libre-soc.org/HDL_workflow/tasyagle/
I got a barebones tasyagle script: https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=7c5a23f1ad0c54862d1b28423dbb87648d15c042 And the issue I'm stuck on. During compilation of distrib/sources/avt libraries, the linker complains about an undefined reference to "errmsg_tab", an external struct. It is defined (but commented out) in avt_lib.h and avt100.h. make[1]: Entering directory '/home/rohdo/src/tas-yagle/distrib/sources/avt' /usr/bin/gcc -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -I/home/rohdo/src/tas-yagle/localinstall/include -g -O3 avt_man.o -o /home/rohdo/src/tas-yagle/distrib/bin/avtman -L/home/rohdo/src/tas-yagle/distrib/lib -lAvt100 -lMut325 -Xlinker -Bstatic -lstdc++ -Xlinker -Bdynamic -lcrypt -lm /usr/bin/ld: /home/rohdo/src/tas-yagle/distrib/lib/libAvt100.a(avt_error.o): in function `avt_initerrmsg': /home/rohdo/src/tas-yagle/distrib/sources/avt/avt_error.c:82: undefined reference to `errmsg_tab' /usr/bin/ld: /home/rohdo/src/tas-yagle/distrib/sources/avt/avt_error.c:70: undefined reference to `errmsg_tab' collect2: error: ld returned 1 exit status make[1]: *** [Makefile:54: /home/rohdo/src/tas-yagle/distrib/bin/avtman] Error 1 make[1]: Leaving directory '/home/rohdo/src/tas-yagle/distrib/sources/avt' make: *** [Makefile:59: avt.compilation] Error 2 I tried to uncomment the struct definition in avt_lib.h, but it lead to a different issue, probably not the right approach is it was commented for a reason.
(In reply to Andrey Miroshnikov from comment #3) > I got a barebones tasyagle script: > https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff; > h=7c5a23f1ad0c54862d1b28423dbb87648d15c042 > > And the issue I'm stuck on. > During compilation of distrib/sources/avt libraries, the linker complains > about an undefined reference to "errmsg_tab", an external struct. It is > defined (but commented out) in avt_lib.h and avt100.h. > /usr/bin/ld: /home/rohdo/src/tas-yagle/distrib/sources/avt/avt_error.c:70: > undefined reference to `errmsg_tab' fun. a struct is not the same as an object *of the type* of a struct. > I tried to uncomment the struct definition in avt_lib.h, but it lead to a > different issue, probably not the right approach is it was commented for a > reason. post the error here for analysis anyway. "a different issue happened" is not useful.
(In reply to Andrey Miroshnikov from comment #2) > (In reply to Luke Kenneth Casson Leighton from comment #1) > > we do not yet have dev-scripts for HITAS/Yagle so that will be needed. > > Marie I will find someone to handle that. Andrey, how about it? > > Will do. > Created the initial script and wiki page, currently setting up. > https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff; > h=f123c4b478e02fcd0d5dd9812b15ab8c54410fa1 i removed the running of the commented out dependencies. they should be listed "please manually run xyz first", see kestrel for examples. > The iwiki page is here: > https://libre-soc.org/HDL_workflow/tasyagle/ excellent. added source link.
list of dependencies from debian/rules: Build-Depends: debhelper (>= 7), quilt, tcsh, texlive-full, swig, libedit-dev, tcl8.5-dev, libmotif-dev, libxp-dev, libxt-dev, libxpm-dev, openjdk-6-jre, libsaxon-java (>= 9), libsaxonb-java, libservlet2.4-java, fop (>= 0.95) don't attempt to add debhelper that is for building debian packages
(In reply to Luke Kenneth Casson Leighton from comment #4) > post the error here for analysis anyway. "a different issue happened" > is not useful. Uncommenting declaration in avt_lib.h #l204: make[1]: Entering directory '/home/rohdo/src/tas-yagle/distrib/sources/avt' /usr/bin/gcc -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -I/home/rohdo/src/tas-yagle/localinstall/include -g -O3 -c -I/home/rohdo/src/tas-yagle/distrib/include -I -I../api/tcl -DAVERTEC -DAVERTEC_DUMMY -DNOFLEX -DAUTO_HEARTBEAT -DLinux -DAVT_H='<avt100.h>' -DMLO_H='<mlo501.h>' -DMUT_H='<mut325.h>' -DRCN_H='<rcn200.h>' -DRPC_SVC_FG -DAVT_VERSION='"3.4"' -DPATCH_NUM='"p5"' -DAVT_DATE_A='"June 7th, 2010"' errmsg.c /usr/bin/ar rv /home/rohdo/src/tas-yagle/distrib/lib/libAvt100.a avt_error.o avt_env.o avt_banner.o avt_trace.o avt_trap.o avt_date.o errmsg.o avt_init_funcs.o avt_license_util.o r - avt_error.o r - avt_env.o r - avt_banner.o r - avt_trace.o r - avt_trap.o r - avt_date.o r - errmsg.o r - avt_init_funcs.o r - avt_license_util.o /usr/bin/ranlib /home/rohdo/src/tas-yagle/distrib/lib/libAvt100.a /usr/bin/gcc -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -I/home/rohdo/src/tas-yagle/localinstall/include -g -O3 avt_man.o -o /home/rohdo/src/tas-yagle/distrib/bin/avtman -L/home/rohdo/src/tas-yagle/distrib/lib -lAvt100 -lMut325 -Xlinker -Bstatic -lstdc++ -Xlinker -Bdynamic -lcrypt -lm /usr/bin/ld: /home/rohdo/src/tas-yagle/distrib/lib/libAvt100.a(avt_error.o): in function `avt_initerrmsg': /home/rohdo/src/tas-yagle/distrib/sources/avt/avt_error.c:82: undefined reference to `errmsg_tab' /usr/bin/ld: /home/rohdo/src/tas-yagle/distrib/sources/avt/avt_error.c:70: undefined reference to `errmsg_tab' collect2: error: ld returned 1 exit status make[1]: *** [Makefile:54: /home/rohdo/src/tas-yagle/distrib/bin/avtman] Error 1 make[1]: Leaving directory '/home/rohdo/src/tas-yagle/distrib/sources/avt' make: *** [Makefile:59: avt.compilation] Error 2 Checked and realised there is no avt100.h, perhaps that was a legacy name. (In reply to Luke Kenneth Casson Leighton from comment #5) > i removed the running of the commented out dependencies. > they should be listed "please manually run xyz first", see kestrel > for examples. I actually copied that comment block from the kestrel script, but removed too much, didn't make it obvious enough.
(In reply to Luke Kenneth Casson Leighton from comment #6) > list of dependencies from debian/rules: > > Build-Depends: debhelper (>= 7), > quilt, no. part of debian build package management > tcsh, hmmm.... unlikely but include it anyway. just don't let it become the default shell > openjdk-6-jre, default-jre-headless *might* cover this
grep -r AVT_H: distrib/share/etc/AVT_libraries.mk:AVT_H = avt100.h distrib/share/etc/libraries.mk:AVT_H = avt$(AVT_LIBVERSION).h looks like it is supposed to be autogenerated AVT_LIBVERSION likely to be 100
I've been able to get tasyagle to compile, however it requires modifying the source code. Ah, also I installed texlive-full (not sure yet if it's absolutely necessary as it's massive, will check later). The location of tcl.h (added when installing tcl8.6-dev) has changed to /usr/include/tcl/tcl.h, and the #include statements in the following files need to be changed to (I guess tcl dir is not in the include variable): #include <tcl/tcl.h> These are the files I needed to change: distrib/sources/yagle/genius/gen_search_global.c distrib/sources/yagle/genius/gen_main.c distrib/sources/api/tcl/eltclsh.h distrib/sources/api/tcl/avt.c distrib/sources/api/tcl/parse.c distrib/sources/api/api/gen_execute_C.c distrib/sources/api/api/api_util.c There is also an auto-generated, but can be changed after the first ./build.sh run: distrib/sources/api/tcl/avt_static_TCL_wrap.c:#include <tcl/tcl.h> It is generated by SWIG, but I haven't found where the paramater for this include is. The SWIG config files (".i" extension) aren't too obvious. Possible config file that seemed to have the settings are: distrib/sources/api/tcl/avtshell_tclsh.i #l44 The terminal output of ./install/bin/xtas: @@@@ @@@@ @@ @ @ @@ @ @@ @@ @ @@ @@@@ @@@@@@ @@ @@@@@@@@ @@ @ @@ @ @@ @@ @@ @@ @@@ @@@ @@ @@@@@ @@@@ @ @@ @@ @@ @@ @@@@ @ @@ @@ @@ @@ @ @@@ @ @@ @@ @ @@ @@@ @@ @@ @@@ @@@@ @@@@ @@@@ @@ @ @@@@@ AVERTEC Release v3.4p5 (64bit) Copyright (c)1998-2022, All Rights Reserved E-mail: support@avertec.com June 7th, 2010
(In reply to Andrey Miroshnikov from comment #10) > The location of tcl.h (added when installing tcl8.6-dev) has changed to > /usr/include/tcl/tcl.h, and the #include statements in the following files if you add "-I/usr/include/tcl" to the Makefiles that's solved.
(In reply to Luke Kenneth Casson Leighton from comment #11) > (In reply to Andrey Miroshnikov from comment #10) > > > The location of tcl.h (added when installing tcl8.6-dev) has changed to > > /usr/include/tcl/tcl.h, and the #include statements in the following files > > if you add "-I/usr/include/tcl" to the Makefiles that's solved. andrey i've added a gitolite3 repo for tas-yagle, please can you push a copy of the gitlab.lip6.fr repo to it, then create a branch, push that as well, and modify the install script to do cd tas-yagle git checkout {whateverbranch} then have a look in distrib/share/etc/Linux.mk ifeq ($(findstring Ubuntu,$(shell uname -v)),Ubuntu) CC += -I/usr/include/tcl8.5 SCC += -I/usr/include/tcl8.5 CPLUSPLUS += -I/usr/include/tcl8.5 endif it should be obvious to cut/paste that to look for Debian and to do tcl8.6 instead $ uname -v #1 SMP Debian 5.10.127-1 (2022-06-30)
(In reply to Luke Kenneth Casson Leighton from comment #12) > andrey i've added a gitolite3 repo for tas-yagle, please can you > push a copy of the gitlab.lip6.fr repo to it, then create a > branch, push that as well, and modify the install script to > do > > cd tas-yagle > git checkout {whateverbranch} Pushed the lastest commit from soc.lip6 into our repo. The script git clones from gitlab.lip6.fr, and adds a libresoc repo and pulls from it. As there are only master branches, what's the "git checkout {whateverbranch}" for? > then have a look in distrib/share/etc/Linux.mk > > it should be obvious to cut/paste that to look for Debian > and to do tcl8.6 instead Figured it out and made the changes. Tomorrow will make sure the script runs correctly in a fresh chroot. Also let me know if there are specific files I can load into the tool to test it.
(In reply to Andrey Miroshnikov from comment #13) > Tomorrow will make sure the script runs correctly in a fresh chroot. The script now works. (Checked that texlive-full is not necessary) Follow the command sequence on the wiki page to compile tas-yagle. Do you want the compiled binary dir to be added to PATH? (there is a script to add the dir to PATH, just haven't got it to work yet)
(In reply to Andrey Miroshnikov from comment #14) > (In reply to Andrey Miroshnikov from comment #13) > > Tomorrow will make sure the script runs correctly in a fresh chroot. > > The script now works. (Checked that texlive-full is not necessary) hoorah. > Follow the command sequence on the wiki page to compile tas-yagle. brilliant. do update it. remove "TODO broken" and also add a direct link to https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=tasyagle-install;hb=HEAD > Do you want the compiled binary dir to be added to PATH? hell no, it's very irritating. the binary needs to be in /usr/local/bin ah. 16 git clone https://gitlab.lip6.fr/vlsi-eda/tas-yagle.git 17 cd tas-yagle 18 git remote add libresoc https://git.libre-soc.org/git/tas-yagle.git 19 git pull libresoc master just 16 git clone https://git.libre-soc.org/git/tas-yagle.git 17 cd tas-yagle
if you can do some research to find out how to override this https://git.libre-soc.org/?p=tas-yagle.git;a=blob;f=build.sh;hb=HEAD 47 # 'Install' 48 mkdir -p install 49 installDir="`pwd`/install" then modify the script: 20 21 ./build.sh 22 to: 21 installDir="/usr/local" ./build.sh then the irritating-ness of having to add to $PATH goes away. it looks like everything's statically-built (otherwise there would be a corresponding ${installDir}/lib copied over
https://www.cyberciti.biz/faq/see-check-if-bash-variable-defined-in-script-on-linux-unix-macos/ this'll do. if [ -z .... ];
(In reply to Luke Kenneth Casson Leighton from comment #15) > (In reply to Andrey Miroshnikov from comment #14) > brilliant. do update it. remove "TODO broken" and > also add a direct link to Done. Added a screenshot of the xtas welcome message as well (image size is small). https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=5d28cb05d97386b93289a9c63ddba5f404cd372d > just > > 16 git clone https://git.libre-soc.org/git/tas-yagle.git > 17 cd tas-yagle Updated. (In reply to Luke Kenneth Casson Leighton from comment #16) > 21 installDir="/usr/local" ./build.sh > > then the irritating-ness of having to add to $PATH goes away. > > it looks like everything's statically-built (otherwise there would > be a corresponding ${installDir}/lib copied over (In reply to Luke Kenneth Casson Leighton from comment #17) > this'll do. if [ -z .... ]; Thanks, added those. https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=eebbda7ff403a64a57c3277297c02fe5091cced0 Anything else need to be done? Do we have any files to feed into the timing analyser?
andrey the path going into avt_tas.sh is borked, /home/lkcl/src/tas-yagle/install/share/tasyag the avt_tas.sh script must create and export AVERTEC_TOP env var based on where tasyag was installed. user can run it once and have that envvar established.
(In reply to Luke Kenneth Casson Leighton from comment #19) > andrey the path going into avt_tas.sh is borked, > /home/lkcl/src/tas-yagle/install/share/tasyag > > the avt_tas.sh script must create and export AVERTEC_TOP env var > based on where tasyag was installed. > > user can run it once and have that envvar established. I made the change for the path in the build.sh script, and added a source statement in .bashrc (although this doesn't seem to work when I start the chroot, only when I call 'bash'). https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=0181a0b966a91e68a9629a26f3cac04b263ec2ce https://git.libre-soc.org/?p=tas-yagle.git;a=commitdiff;h=6554252c5e6466d4f6bca5722efb2d6f30ab0128 In IRC you also mentioned documentation generation, I'll start looking into that now. https://libre-soc.org/irclog/latest.log.html#t2022-07-21T17:39:56
(In reply to Andrey Miroshnikov from comment #20) > I made the change for the path in the build.sh script, and added a source > statement in .bashrc (although this doesn't seem to work when I start the > chroot, only when I call 'bash'). sounds about right, sigh. > In IRC you also mentioned documentation generation, I'll start looking into > that now. probably what texlive was for. you'll then have a tutorial to check what's going on.
Had to change the AVERTEC_TOP variable back to what it was (all the doc scripts expect it to be in the tas-yagle repo dir), and added distrib/bin to PATH (some doc makefiles use binaries from there). https://git.libre-soc.org/?p=tas-yagle.git;a=commitdiff;h=11fa2abc9618fd78f8d5ceabe670ef4a5713d1e8 https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=2cdf7cb9a9f398327bf6ce0e84ab3e494a128b69 Calling "make" in distrib/docxml2/ I get an error about java: make -C text/doc/hitas_reference all make[1]: Entering directory '/home/rohdo/src/tas-yagle/distrib/docxml2/text/doc/hitas_reference' cat filename.xsl > /home/rohdo/src/tas-yagle/distrib/share/../docxml2/pdf/file.xsl echo "<xsl:param name=\"release_num\">"3.4""p5"</xsl:param>" >> /home/rohdo/src/tas-yagle/distrib/share/../docxml2/pdf/file.xsl echo "<xsl:param name=\"date\">"June 7th, 2010"</xsl:param>" >> /home/rohdo/src/tas-yagle/distrib/share/../docxml2/pdf/file.xsl echo "<xsl:param name=\"pictpdf\">/home/rohdo/src/tas-yagle/distrib/share/../docxml2/imgs_pdf</xsl:param></xsl:stylesheet>" >> /home/rohdo/src/tas-yagle/distrib/share/../docxml2/pdf/file.xsl /usr/lib/jvm/java-1.6.0-openjdk/bin/java -jar /usr/share/java/saxon9.jar hitas_reference.xml /home/rohdo/src/tas-yagle/distrib/share/../docxml2/pdf/genPDF.xsl > hitas_reference.fo /bin/sh: 1: /usr/lib/jvm/java-1.6.0-openjdk/bin/java: not found make[1]: *** [Makefile:96: /home/rohdo/src/tas-yagle/distrib/share/../docxml2/compiled/docpdf/hitas_reference.pdf] Error 127 make[1]: Leaving directory '/home/rohdo/src/tas-yagle/distrib/docxml2/text/doc/hitas_reference' make: *** [Makefile:13: all] Error 2
(In reply to Andrey Miroshnikov from comment #22) > Had to change the AVERTEC_TOP variable back to what it was (all the doc > scripts expect it to be in the tas-yagle repo dir), and added distrib/bin to > PATH (some doc makefiles use binaries from there). > > https://git.libre-soc.org/?p=tas-yagle.git;a=commitdiff; > h=11fa2abc9618fd78f8d5ceabe670ef4a5713d1e8 echo "PATH=`pwd`/distrib/bin:${AVERTEC_TOP}/tcl:${PATH}" >> "${installDir}/avt_env.sh" to avoid substituting AVERTEC_TOP and PATH too early, that should probably be: echo "PATH=`pwd`/distrib/bin"':${AVERTEC_TOP}/tcl:${PATH}' >> "${installDir}/avt_env.sh"
(In reply to Jacob Lifshay from comment #23) > to avoid substituting AVERTEC_TOP and PATH too early, that should probably > be: Thanks Jacob, that fixed the env var expansion issue. (In reply to Andrey Miroshnikov from comment #22) Also managed to fix the error during document generation, which required setting jdk path to default (instead of specific version), and for saxon (XSLT processor). https://git.libre-soc.org/?p=tas-yagle.git;a=commitdiff;h=e1478977c186762c0b8e69c19b68379c8b6eb83d However now there's an error with XSLT: /usr/lib/jvm/default-java/bin/java -jar /usr/share/java/saxon.jar hitas_reference.xml /home/rohdo/src/tas-yagle/distrib/share/../docxml2/pdf/genPDF.xsl > hitas_reference.fo Error at xsl:for-each on line 893 of file:/home/rohdo/src/tas-yagle/distrib/share/../docxml2/pdf/genPDF.xsl: Error in expression tokenize(msg,'\\n'): Unknown system function: tokenize Transformation failed: Run-time errors were reported make[1]: *** [Makefile:96: /home/rohdo/src/tas-yagle/distrib/share/../docxml2/compiled/docpdf/hitas_reference.pdf] Error 2 make[1]: Leaving directory '/home/rohdo/src/tas-yagle/distrib/docxml2/text/doc/hitas_reference' make: *** [Makefile:13: all] Error 2 Line 893 of distrib/docxml2/pdf/genPDF.xsl: <xsl:for-each select="tokenize(msg,'\\n')"> The version of saxon on my Debian chroot is 6.5.5, here the documentation for this function: http://saxon.sourceforge.net/saxon6.5.5/xsl-elements.html#xsl:for-each Does "Unknown system function:" mean anything to you?
https://www.google.com/search?q=Error+in+expression+tokenize(msg%2C%27%5C%5Cn%27)%3A+Unknown+system+function%3A+tokenize+saxon+xslt https://stackoverflow.com/questions/67014840/tokenize-is-an-unknown-xslt-function https://www.oxygenxml.com/forum/post47861.html
(In reply to Luke Kenneth Casson Leighton from comment #25) > https://www.google.com/ > search?q=Error+in+expression+tokenize(msg%2C%27%5C%5Cn%27)%3A+Unknown+system+ > function%3A+tokenize+saxon+xslt > Thanks Luke, I realised the issue was with the XSLT 2.0 support. The Saxon 6.5.5 only supports 1.0. Using Saxon-B allows XSLT 2.0 (but also need to use the -ext:on option to allow extension functions): https://git.libre-soc.org/?p=tas-yagle.git;a=commitdiff;h=e1777fa93c53e967e6b3587202759dd4c7a9aafd The docs now compile, and you'll find the corresponding HTML and PDF docs here: distrib/docxml2/compiled/dochtml distrib/docxml2/compiled/docpdf After a bit of fiddling, was able to source the env vars needed for doc generation. The docs are now compiled after compiling the software: https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=bae2009ffc5a3aa630990943abc825585f6927ae Now on to reading the docs :)
Been trying to get the basic inverter example to work. The example is located here: distrib/share/tutorials/hitas/inv Chapter 5 Inverter example of hitas_tutorial.pdf goes over the db.tcl tcl file used to generate the DTX, STM, and RCX databases (these are then used by the "xtas" program). To generate the databases, the user has to run the db.tcl script: ./db.tcl (some other tests instead use 'run.tcl') Here's the output: Loading Spice netlist "./inv.spi" Check level I (connectors) @@@@ @@@@ @ @@@@@@@@@@ @@ @@ @@@ @ @@ @ @@ @@ @ @ @@ @ @@ @@ @@ @@@@ @@@@@@ @@ @@ @@@@ @@ @@ @ @@ @ @@@@@@@@@ @@ @@ @@ @@ @@@ @@ @@ @@ @@ @@@@@ @@@@ @@ @@ @@ @@ @@ @@ @@@@ @@ @@ @@ @@ @@ @@ @ @@@ @@ @@ @@ @@ @@ @@@ @@ @@ @@@@ @@@@ @@@@@@ @@@@@@ @@@@ @@ @ @@@@@ AVERTEC Release v3.4p5 (64bit) Copyright (c)1998-2022, All Rights Reserved E-mail: support@avertec.com June 7th, 2010 LOADING FILE inv 00min 00s hitas user : 00'00.0'' system : 00'00.0'' ----------------------------------- DISASSEMBLING: Check level II (nets) Transistor netlist checking 00m00s u:00m00.0 M:24296Kb Extracting CMOS duals 00m00s u:00m00.0 M:24660Kb Check level III (cones) Extracting bleeders 00m00s u:00m00.0 M:24660Kb Making gates 00m00s u:00m00.0 M:24660Kb Latches detection 00m00s u:00m00.0 M:24660Kb Making cells 00m00s u:00m00.0 M:24660Kb External connector verification 00m00s u:00m00.0 M:24660Kb Checking the yagle figure 00m00s u:00m00.0 M:24660Kb ------------------------------------------------------------ See file 'inv.rep' for more information ------------------------------------------------------------ 00min 00s hitas user : 00'00.0'' system : 00'00.0'' ----------------------------------- CNS FILE inv.cns: 00min 00s hitas user : 00'00.0'' system : 00'00.0'' ----------------------------------- COMPUTING GATE DELAYS: 00min 00s hitas user : 00'00.0'' system : 00'00.0'' ----------------------------------- [Fatal Internal Error AVT-027]: Internal error, please contact Avertec support The error occurs on line 19 of db.tcl, when calling 'hitas inv' tcl command. This command pulls in the inv.spi spice file, and the error seems to be due to declaration of the transistors used for the inverter: MM02 y a gnd gnd tn L=0.18U W=1.15U AS=0.414P AD=0.414P PS=3.02U PD=3.02U NF=20 MM03 y a vdd vdd tp L=0.18U W=2.23U AS=0.8028P AD=0.8028P PS=5.18U PD=5.18U NF=20 Removing the parameters PS and PD (Source and Drain Perimeters, used to calculate parasitic diode and capacitance) change the error to: COMPUTING GATE DELAYS: [Warning TRC-010]: The equivalent gate output load gives a negative capacitance for signal y. 0 value is retained [Error TRC-005]: Internal error #46 on net y. ** TOTAL ERRORS: 1 ** TOTAL WARNINGS: 1 I'm not sure how to proceed, because I don't know what causes the Internal error (AVT-027). As I started writing this comment, I also ran the other tutorial tests. addaccu, adder, blackbox, cpu2901, inv, lag, library, mipsr3000, ms, multicycle, other_examples/hierarchy,mult,shift gives the same error as above (AVT-027). The other tutorials: clock_gating, counter, are stuck (or it takes more than 10min) : FLATENNING THE FIGURE h_macro has a test related to RC cache: [Error MBK-006]: Can't flatten figure top because RC cache is active ** TOTAL ERRORS: 1 ** TOTAL WARNINGS: 1 ssta/adder I'll start running now (it has monter-carlo statistical sim, so takes a while). I checked the log of the build.sh script, however I saw no warnings or errors. It looks likes something is missing or not configured however.
(In reply to Andrey Miroshnikov from comment #27) > The other tutorials: clock_gating, counter, leave them running. it is analog simulation.
(In reply to Andrey Miroshnikov from comment #27) > Been trying to get the basic inverter example to work. The example is > located here: > distrib/share/tutorials/hitas/inv Hello Andrey, I didn't follow closely your rebuild efforts, but did you use the system-wide flex or the 2.5.4 version supplied with Tas/Yagle sources? I am not a hundred percent sure, but I seems to recall that using any other version of flex produce what you are observing. This is, of course, a bug, but one we cannot solve right now, because it implies to completely trace down the Yacc/Lex parsers (Bison/Flex). Best,
(In reply to Jean-Paul Chaput from comment #29) > I didn't follow closely your rebuild efforts, but did you use the > system-wide flex or the 2.5.4 version supplied with Tas/Yagle sources? > I am not a hundred percent sure, but I seems to recall that using any > other version of flex produce what you are observing. Tested in a fresh debian 10 chroot to make sure the tas-yagle 2.5.4 flex is used. Removed 'flex' package from the "install-hdl-apt-reqs" script (installs typical build/lang packages). The output of running the inverter ./db.tcl has now changed: LOADING FILE inv 00min 00s hitas user : 00'00.0'' system : 00'00.0'' ----------------------------------- DISASSEMBLING: Check level II (nets) Transistor netlist checking 00m00s u:00m00.0 M:25288Kb Extracting CMOS duals 00m00s u:00m00.0 M:25584Kb Check level III (cones) Extracting bleeders 00m00s u:00m00.0 M:25584Kb Making gates 00m00s u:00m00.0 M:25584Kb Latches detection 00m00s u:00m00.0 M:25584Kb Making cells 00m00s u:00m00.0 M:25584Kb External connector verification 00m00s u:00m00.0 M:25584Kb Checking the yagle figure 00m00s u:00m00.0 M:25584Kb ------------------------------------------------------------ See file 'inv.rep' for more information ------------------------------------------------------------ 00min 00s hitas user : 00'00.0'' system : 00'00.0'' ----------------------------------- CNS FILE inv.cns: 00min 00s hitas user : 00'00.0'' system : 00'00.0'' ----------------------------------- COMPUTING GATE DELAYS: [Warning TRC-010]: The equivalent gate output load gives a negative capacitance for signal y. 0 value is retained [Error TRC-005]: Internal error #46 on net y. ** TOTAL ERRORS: 1 ** TOTAL WARNINGS: 1 Output of inv.rep: [WRN 01] VSS connector detected (0.000V) : 'gnd' [WRN 01] VDD connector detected (1.620V) : 'vdd'
(In reply to Andrey Miroshnikov from comment #30) > Tested in a fresh debian 10 chroot to make sure the tas-yagle 2.5.4 flex is > used. Removed 'flex' package from the "install-hdl-apt-reqs" script > (installs typical build/lang packages). whatever tou do under no circumstances commit that as a change to install-hdl-apt-reqs. it is good for testing but unnecessary as installation an alternative version should be in local PATH with local INCLUDES in the Makefile. if flex provides a pc-config file, everything is runtime-detectable by the Makefile as long as you provide the correct pc-config file. it is however useful for JP to know that the local version is actually being used by hard-removing the system-wide one. for future reference all you had to do was add "apt-get remove flex" to the hitas script.
(In reply to Luke Kenneth Casson Leighton from comment #31) > whatever tou do under no circumstances commit that as a change to > install-hdl-apt-reqs. Of course, I wasn't even planning on it :) The only reason I tried that way is because I was seeing a different problem when doing "apt purge" (until I realised that the extra env vars weren't being source'd). To re-iterate - I will *NOT* be modifying - install-hdl-apt-reqs. > for future reference all you had to do was add "apt-get remove flex" > to the hitas script. Sure, that's what I'll do for the tasyagle-install script.
Added the apt purge flex. There was also a missing groff dep for docs. See the latest script commit here: https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=626f0870d7d6d52e17225e7cf69087c1196632fc No progress has been made on the inv example issue: [Fatal Internal Error AVT-027]: Internal error, please contact Avertec support The install script definitely uses the provided flex version (as the system version was deleted). The libre-soc git repo for tas-yagle: https://git.libre-soc.org/?p=tas-yagle.git;a=summary Do you have any ideas Marie?
Added a section to the tasyagle wiki page about the tutorials (Section 2.3): https://libre-soc.org/HDL_workflow/tasyagle/
Changed the location of avt_env shell script (which loads AVERTEC_TOP and PATH) to /usr/local/bin/ (to comply with Filesystem Hierarchy Standard or FHS). https://git.libre-soc.org/?p=tas-yagle.git;a=commitdiff;h=46131a24099cfcd0fdfa1638ed1c53d6935d76b2 Also updated the dev-env script likewise: https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=4cfb749e95fa02b065e0d726d75c8692423c652b
As an experiment, tried to setup an Ubuntu chroot (to see if the tas-yagle building works). Currently struggling with adding backports to bionic (the version of Ubuntu I found available on http://archive.ubuntu.com/ubuntu). Trying to update the packages, I get a problem with unknown source: W: Skipping acquire of configured file 'bionic-backports/source/Sources' as repository 'http://archive.ubuntu.com/ubuntu bionic InRelease' doesn't have the component 'bionic-backports' (component misspelt in sources.list?) Here's what I have in /etc/apt/sources.list: deb http://archive.ubuntu.com/ubuntu bionic main bionic-backports deb-src http://archive.ubuntu.com/ubuntu/ bionic main bionic-backports
(In reply to Andrey Miroshnikov from comment #36) > As an experiment, tried to setup an Ubuntu chroot (to see if the tas-yagle > building works). > > Currently struggling with adding backports to bionic don't. no point. > Here's what I have in /etc/apt/sources.list: > deb http://archive.ubuntu.com/ubuntu bionic main bionic-backports > deb-src http://archive.ubuntu.com/ubuntu/ bionic main bionic-backports drop those. just bionic. canonical do not do backports.
(In reply to Luke Kenneth Casson Leighton from comment #37) > drop those. just bionic. canonical do not do backports. actually, they totally do have backports: https://packages.ubuntu.com/bionic-backports/ from my /etc/apt/sources.list (i'm on focal, not bionic) ## N.B. software from this repository may not have been tested as ## extensively as that contained in the main release, although it includes ## newer versions of some applications which may provide useful features. ## Also, please note that software in backports WILL NOT receive any review ## or updates from the Ubuntu security team. deb http://us.archive.ubuntu.com/ubuntu focal-backports main restricted universe multiverse # deb-src http://us.archive.ubuntu.com/ubuntu focal-backports main restricted universe multiverse
(In reply to Jacob Lifshay from comment #38) > (In reply to Luke Kenneth Casson Leighton from comment #37) > > drop those. just bionic. canonical do not do backports. > > actually, they totally do have backports: they are not the least bit necessary.
Comparison results of Static Timing Analysis (HiTas) and transistor-level simulation (ngspice) using a "dummy" cmos technology. Use case: invertoer and inverter chain showing how to configure the tools and provide results. Evaluation results could be rebuilt with : * alliance-check-toolkit commit #6d03d407 Inverter timing analysis ------------------------- A. With STA ++++++++++++ Running: 1. Building the timing database ./hitas/db_ng.tcl NB. here, Hitas uses inv.spi description of the netlist to detect VDD and VSS (see inv.rep) 2. Report critical paths ./hitas/report_inv_ng.tcl provides the inv.paths file that shows the 2 paths of the inverter. +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 20 | 51 +-------+--------+--------------+-----------------------+ | R | F | 20 | 40 +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results in ps. B. With transistor level simulator ngspice ++++++++++++++++++++++++++++++++++++++++++ ngpsice top_inv.spi displays timing plots with information of input slope and propagation delay : +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 20 | 36 +-------+--------+--------------+-----------------------+ | R | F | 20 | 30 +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results in ps. showing that STA delays are greater than simulation delays, keeping the relative order, with an error for STA of : 30% in the worse case. Inverter chain timing analysis ------------------------------ A. With STA ++++++++++++ Running: 1. Building the timing database ./hitas/db_chain_ng.tcl NB. here, Hitas uses inv_chain.spi description of the netlist to detect VDD and VSS (see inv_chain.rep) 2. Report critical paths ./hitas/report_chain_ng.tcl provides the inv_chain.paths file that shows the 2 paths of the inverter chain. +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 20 | 439 +-------+--------+--------------+-----------------------+ | R | F | 20 | 397 +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results in ps. 3. Other analysis with the Hitas GUI: Xtas xtas file/open inv_chain.dtx Tools/Get Paths Select path/path Detail B. With transistor level simulator ngspice ++++++++++++++++++++++++++++++++++++++++++ ngpsice top_inv_chain.spi displays timing plots with information of input slope and propagation delay : +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 20 | 395 +-------+--------+--------------+-----------------------+ | R | F | 20 | 377 +-------+--------+--------------+-----------------------+ showing that STA delays are greater than simulation delays, keeping the relative order, with an error for STA of : 10% in the worse case.
Created attachment 174 [details] ngspice timing plot of the inverter chain Timing plot of the inverter chain, in cmos dummy technology, simulated with ngspice, can be reproduced with * alliance-check-toolkit commit #6d03d407
Created attachment 175 [details] Timing paths provided by HiTas Static Timing Analysis results provided by HiTas Use case : inverter technology: dummy cmos Configuration and files to reproduce the results may be found: * alliance-check-toolkit commit #6d03d407
Created attachment 176 [details] Tiiming paths provided by HiTas for the inverter chain Static timing analysis results provided by HiTas Use case: inverter chain Technology: dummy cmos results can be reproduced using configuration files in * alliance-check-toolkit #6d03d407
Comparison results of Static Timing Analysis (HiTas) and transistor-level simulation (ngspice) using the cmos Sky130 technology. Use case: inverter and inverter chain showing how to configure the tools and provide results. Evaluation results could be rebuilt with : * alliance-check-toolkit commit #6d03d407 Inverter timing analysis ------------------------- A. With STA ++++++++++++ Running: 1. Building the timing database ./hitas/db_ng.tcl NB. here, Hitas uses inv_x2_hitas.spi description of the netlist to detect VDD and VSS (see inv_x2.rep) 2. Report critical paths ./hitas/report_inv_ng.tcl provides the inv_x2.paths file that shows the 2 paths of the inverter. +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 8 | 10 +-------+--------+--------------+-----------------------+ | R | F | 8 | 8 +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results in ps. B. With transistor level simulator ngspice ++++++++++++++++++++++++++++++++++++++++++ ngpsice top_inv_x2.spi displays timing plots with information of input slope and propagation delay : +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 8 | 7.15 +-------+--------+--------------+-----------------------+ | R | F | 8 | 6.95 +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results in ps. showing that STA delays are greater than transistor simulation delays, keeping the relative order, with an error for STA of : 28% in the worse case. Inverter chain timing analysis ------------------------------ A. With STA ++++++++++++ Running: 1. Building the timing database ./hitas/db_chain_ng.tcl NB. Here, Hitas uses inv_x2_chain_hitas.spi description of the netlist to detect VDD and VSS (see inv_x2_chain.rep) 2. Report critical paths ./hitas/report_chain_ng.tcl provides the inv_x2_chain.paths file that shows the 2 paths of the inverter chain. +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 8 | 93 +-------+--------+--------------+-----------------------+ | R | F | 8 | 89 +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results in ps. 3. Other analysis with the Hitas GUI: Xtas xtas file/open inv_x2_chain.dtx Tools/Get Paths Select path/path Detail B. With transistor level simulator ngspice ++++++++++++++++++++++++++++++++++++++++++ ngpsice top_inv_x2_chain.spi displays timing plots with information of input slope and propagation delay : +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 8 | 87 +-------+--------+--------------+-----------------------+ | R | F | 8 | 85 +-------+--------+--------------+-----------------------+ showing that STA delays are greater than simulation delays, keeping the relative order, with an error for STA of : 6% in the worse case.
Created attachment 177 [details] ngspice timing plot of the inverter chain - Sky130cmos Timing plot of the inverter chain, in cmos SkY130 technology, simulated with ngspice, can be reproduced with * alliance-check-toolkit commit #6d03d407
Created attachment 178 [details] Timing paths provided by HiTas - inverter - Sky130 Static Timing Analysis results provided by HiTas Use case : inverter technology: cmos Sky130 Library : C4M-Sky130 Configuration and files to reproduce the results may be found: * alliance-check-toolkit commit #6d03d407
Created attachment 179 [details] Tiiming paths provided by HiTas - inverter chain - Sky130 Static Timing Analysis results provided by HiTas Use case : inverter chain technology: cmos Sky130 Library : C4M-Sky130 Configuration and files to reproduce the results may be found: * alliance-check-toolkit commit #6d03d407
Comparison results of Static Timing Analysis (HiTas) and transistor-level simulation using an NDA 180nm cmos technology. Use case: C4M-FlexLib inverter and inverter chain showing how to configure the tools and provide results. Evaluation results could be rebuilt with : * alliance-check-toolkit commit #6d03d407 and your NDA-PDK. Inverter Analysis -------------------- A. With STA ++++++++++++ Running: 1. Building the timing database ./hitas/db.tcl NB. here, Hitas uses inv_x2_hitas.spi description of the netlist to detect VDD and VSS (see inv_x2.rep) 2. Report critical paths ./hitas/report_inv.tcl provides the inv_x2.paths file that shows the 2 paths of the inverter. +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 5 | NDA +-------+--------+--------------+-----------------------+ | R | F | 5 | NDA +-------+--------+--------------+-----------------------+ where F: falling, R: rising. B. With transistor level simulator eldo (Siemens EDA software) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ eldo top_eldo.spi displays the delays (input slope and propagation delay) and write them in the file top_eldo.chi and ezwave displays timing plots +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 5 | NDA +-------+--------+--------------+-----------------------+ | R | F | 5 | NDA +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results. showing that STA delays are greater than simulation delays, keeping the relative order, with an error for STA of : 6% in the worse case. Inverter chain timing analysis ------------------------------ A. With STA ++++++++++++ Running: 1. Building the timing database ./hitas/db_chain.tcl NB. Here, Hitas uses inv_x2_chain_hitas.spi description of the netlist to detect VDD and VSS (see inv_x2_chain.rep) 2. Report critical paths ./hitas/report_chain.tcl provides the inv_x2_chain.paths file that shows the 2 paths of the inverter chain. +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 5 | NDA +-------+--------+--------------+-----------------------+ | R | F | 5 | NDA +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results. 3. Other analysis with the Hitas GUI: Xtas xtas file/open inv_x2_chain.dtx Tools/Get Paths Select path/path Detail B. With transistor level simulator eldo (Siemens EDA software) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ eldo top_chain_eldo.cir displays the delays (input slope and propagation delay) and write them in the file top_chain_eldo.chi and ezwave displays timing plots +-------+--------+--------------+-----------------------+ | input | output | input slope | propagation delay +=======+========+==============+=======================+ | F | R | 5 | NDA +-------+--------+--------------+-----------------------+ | R | F | 5 | NDA +-------+--------+--------------+-----------------------+ where F: falling, R: rising, timing results. showing that STA delays are slightly smaller than simulation delays, keeping the relative order, with an error for STA of : 4% in the worse case.
Configuration files for static timing analysis and simulation in the case of a small digital FSM, showing the 5 longest paths and setup/hold timing data using the cmos 180nm under NDA are available in : * alliance-check-toolkit commit #6b5a0ee9 they can be reproduced with the appropriate NDA-PDK
Configuration files for static timing analysis and simulation of eth_spram_256x32 showing the 5 longest paths and setup/hold timing data for connector addr[] using the cmos SkyWater130 PDK are available in : * alliance-check-toolkit commit #e5f4c777 Results can be reproduced with: * coriolis commit #288d1c70 * alliance-check-toolkit commit #e5f4c777
Created attachment 181 [details] Static Timing Analysis of spram_256x32 Static Timing Analysis of spram_256x32 Target process : SkyWater130 Standard Cells : C4M-Sky130 Showing 5th longest paths provided by HiTas
(In reply to Marie-Minerve Louerat from comment #50) > Configuration files for static timing analysis and simulation > of eth_spram_256x32 fantastic, thank you marie-minerve > Results can be reproduced with: > > * coriolis commit #288d1c70 > * alliance-check-toolkit commit #e5f4c777 https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/288d1c70 https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/commit/e5f4c777a351cc42a03c898607deee5a3da15061
Transistor models appropriate for simulation with ngspice and for static timing analysis are provided in alliance-check-toolkit Target process : SkyWater130 * alliance-check-toolkit commit #8d679b20
Update static timing analysis scripts of a small FSM Process: SkyWater130 Standard Cells : C4M-FlexCell lib The study (synthesis, P&R, simulation, STA) can be performed using: * Coriolis commit #288d1c70 * alliance-check-toolkit commit #8d679b20 and going to benchs/SAR directory, following the README.rst instructions.
Update scripts for static Timing Analysis of spram_256x32 Static Timing Analysis of spram_256x32 Target process : SkyWater130 Standard Cells : C4M-FlexCell lib Transistor model for HiTas : BSIM4 SkyWater130, level = 14 Showing 5th longest paths provided by HiTas and other timing data : setup and hold times, timing access of output. The study (synthesis, P&R, simulation, STA) can be reproduced using: * Coriolis commit #288d1c70 * alliance-check-toolkit commit #8d679b20 and benchs/spram_256x32/sky130_c4m directory, following the README_timing.rst instructions.
Static Timing Analysis of another SRAM architecture. With optimized P&R. The configuration and scripts are available in : https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/commit/4fa1186cd99b3d2954fb2b8fcd131d26cfbe2bd8 SRAM is 256x32 Using SkyWater130 process C4M-FlexCell library Results can be reproduced with : * coriolis commit #288d1c70 * alliance-check-toolkit commit #4fa1186c following the README_timing.rst flow
Created attachment 182 [details] Static Timing Analysis of SRAM 256x32 SkyWater130 10 longest paths are reported
Created attachment 183 [details] STA of SRAM - 256x32 - SkyWater130 - Slack report
Static Timing Analysis of the SRAM architecture. With optimized P&R (regular). The configuration and scripts are available in : https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/commit/84b388879e793c9f3da427b2016d34f694f2644f SRAM is 256x32 Using TSMC 180 process C4M-FlexCell library Results can be reproduced with : * coriolis commit #288d1c70 * alliance-check-toolkit commit #84b38887 following the README_timing.rst flow and using TSMC180 PDK (under NDA)
Created attachment 184 [details] Flow and files generated to perform Static Timing Analysis of SRAM