placeholder. APPROVED. TODO: define tasks for MoU
* Porting PDKMaster to Sky130, including flow, simulations setup, design rules, ...: 3500EUR.
* Std. cell library optimization, more area efficiency + timing investigation: 1000EUR
* IO library: 125MHz operation + multiplexing capability in test chip for ULPI/RGMII: 2500EUR
* flexram SRAM on Sky130, two options
* single block: 750EUR
* compiler that can generate different blocks: 1500EUR
We need to first define what one actually want to test and who does what.
Test only functional through JTAG patterns provided to me or full test on ethernet and USB functionality ?
Will there be PCB needed with ethernet PHY and/or USB PHY ?
So budget needed may go from 1000EUR to 5000EUR I would say.
Top level bugs:
* bug #630 - Skywater 130nm PDKMaster
Draft instructions partially designed: